Huawei first names Kirin 9000S as processor in Mate 60 Pro model

The automotive chip company XHEART, established as part of the Momenta chip program, unveiled its X7 Ultra chip on October 29. The company positions this chip as a solution specifically designed to work with large control models, estimating its computational power for such tasks at 700 TOPS.

The head of XHEART noted that the development began with the observation that driver assistance software is shifting from numerous small models to a single, comprehensive large model, which requires corresponding chip adaptation. When the company was founded in 2023, the decision was made to work in reverse, starting from the models actually used in vehicles, and organizing computation, memory, and data movement around them, leaving room for future models.

The X7 Ultra is equipped with a very large NPU core. XHEART claims that data transfer within a single core occurs orders of magnitude faster, reaching terabytes per second, compared to data transfer between cores. A multi-level cache, designed for high throughput and parallelism, aims to reduce inference latency and power consumption. A specialized operator engine accelerates key Transformer operations, such as LayerNorm, Softmax, and Transpose, and also supports FP16 and FP32 vector mathematics to maintain model accuracy.

According to the company's data, production models running on the chip meet benchmark results with 99.99 percent accuracy, and compute utilization reaches 98.7 percent. Compared to products the company calls industry flagships, XHEART states an 80 percent reduction in memory bandwidth consumption and a doubling of energy efficiency. These figures are presented by the company itself and have not undergone independent testing.

The chip also includes, according to XHEART, China's first mass-produced automotive Armv9 processor, which demonstrates 20 percent higher performance and 10 percent better energy efficiency. The architecture with a large cluster improves the coordination of multi-core processors and access to L3 memory, while the new SVE2 vector engine provides higher signal processing performance compared to the previous generation NEON.

XHEART also demonstrated its next chip. The X9 model targets 3000 TOPS for large model computations and 700 GB/s memory bandwidth per chip, with its release planned for 2027. It will be developed jointly with next-generation world-class models, synchronizing computation and memory access for efficient operation of larger models.

The company reports being in a cycle of producing one generation, developing the next, and researching a third. Two years have passed from its founding until mass production. The first X7 chip was operational within 24 hours of returning from the factory, and on the 17th day, the chip, low-level software, and control model were working together in a full vehicle.

Chery unveiled its Ziwei line of automotive chips at the global innovation conference held on October 20. This portfolio includes C series central computing chips, S series silicon carbide automotive chips, and M series vehicle control chips, thereby expanding the automaker's semiconductor development in computing and power electronics.

The C100 central computing chip is designed to implement physical artificial intelligence directly on the device. According to Chery, a vehicle configuration with two neural processors can achieve up to 2400 TOPS with a memory bandwidth of 600 GB per second, enabling the support of real-world models with 100 billion parameters.

Furthermore, the S1500 silicon carbide product supports a nominal voltage of 1500 V. Chery also announced that its eight-inch silicon carbide wafers have entered mass production, allowing for a cost reduction of over 30%, and demonstrated five families of chip packaging developed to cover the company's platforms.

WuXi Stars Micro System Technologies has introduced three interconnect chips designed for artificial intelligence clusters and servers. The company, founded in 2020, held its first full-stack and brand product launch in Uxi on October 15, demonstrating 12 interconnect chips that are already in mass production alongside new components.

The centerpiece of the presentation was the C82-4G, which the company named the first PCIe 6.0 switch developed in China. It is capable of supporting up to 144 lanes at 64 GT/s per lane, doubling the per-lane speed of PCIe 5.0. The switch utilizes PAM4 signaling and FLIT mode, ensuring non-blocking switching with a latency in the range of 100 nanoseconds, as well as support for fabric networking, CXL memory expansion, and memory pooling. It is designed for internal connections in next-generation AI servers, where switches extend processor PCIe lanes to GPUs, network cards, and solid-state drives.

The second product is an 800G multi-protocol AI network card, which the company positions as the first such development from a Chinese supplier. This card incorporates a PCIe Gen6 switch with 48 lanes, supports 800G line-rate transmission with microsecond-level latency, offloads RoCE v2, and offers programmable congestion control. The company notes that the card is optimized for Hygon processors and next-generation supernode architectures focused on inter-node communication in clusters comprising tens of thousands of accelerators.

The third component presented is a multi-mode RAID chip, created using domestic intelligent capabilities. It supports SAS, SATA, and PCIe 5.0 connections, is compatible with both hard drives and SSDs, features a hardware encryption block, and, according to the company, increases throughput and IOPS by approximately eight times compared to the previous generation.

CEO Guo Erhui emphasized that computing power is a system of tightly coupled components: computation, networking, data storage, power, cooling, and planning. He noted that as clusters grow to tens of thousands of cards, interconnects become the bottleneck. The company reported that its products are already used in the internet, finance, telecommunications, and energy sectors, with stated failure rates for the chips being less than 100 DPPM, and for the boards being less than 500 DPPM.

During the launch, cooperation agreements were signed with Kylin Software, UnionTech, Tencent Cloud, Inspur, H3C, ZTE, and Lenovo. These agreements cover the adaptation of the company's interconnect chips to their operating systems and server platforms. The company stated that future steps include the mass production of the next-generation network card and PCIe 6.0 switch, as well as work on optical interconnects and storage pooling. It should be noted that all stated specifications are company claims and have not undergone independent verification.