MemTensor releases open-source MemT 1.0 model with memory for preserving long histories
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Pandaily
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MemTensor releases open-source MemT 1.0 model with memory for preserving long histories

The Chinese company MemTensor has introduced and made publicly available a series of models it calls memory-oriented foundation models, named MemT 1.0. This series includes two models: MemT-1.0-Flash, which has a total of 288 billion parameters, of which 17 billion are actively used, and MemT-1.0-Nano, which has 36 billion total parameters and 3 billion active ones.

The weights of these models are available on the Hugging Face platform, and the corresponding code is hosted on GitHub along with a technical report.

The models are designed to solve a common problem associated with long dialogues. Most existing systems store the entire history in the context window, which leads to slowdowns and increased inference costs with every new turn. Instead, MemT integrates a trainable memory module directly into the model.

After each interaction, the model records new information into a fixed memory state and retrieves it when necessary, instead of re-reading the entire previous log every time.

MemTensor reports that the training of the models was conducted in two stages based on 34 billion tokens: first, the model learned to write information into memory, and then it learned to answer questions using this stored information.

Performance Results and Comparison

All presented performance metrics are based on the company's own evaluation. MemTensor claims that end-to-end inference runs approximately 1.86 times faster than the full context approach with a history of 128 thousand tokens, and about 3.99 times faster with 256 thousand tokens.

The time to the first token response is estimated at approximately 104–112 milliseconds for the memory model, compared to approximately 445 milliseconds for full context at 256K. Furthermore, the company notes that the memory state size per session with a 256K history is about 40 MB, which is significantly less than the 5.06 GB required for the full context cache, representing a reduction of approximately 130 times.

On 11 memory benchmarks, MemTensor reports average scores of 50.6 for Flash and 47.0 for Nano. These results place the models first and second among comparable parametric memory methods and roughly match the results of retrieval-augmented approaches on average, even without retrieving history during the query.

The company also emphasizes that adding memory did not degrade the overall capabilities of the Flash model under tests with a high number of distractors.

Developers should note the licensing terms: the repository code is published under the non-commercial PolyForm license, while the model weights have Apache and MIT licenses, respectively.

The team plans further development towards improving long-term memory, increasing memory capacity, and reducing memory update costs, with the long-term goal of creating agents that continue to learn based on their interactions.

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MemSilicon introduced the MountTai 2026 RRAM chip with a 1T4R architecture
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pandaily.com

MemSilicon introduced the MountTai 2026 RRAM chip with a 1T4R architecture

The Chinese memory startup MemSilicon announced the completion of the tape-out process for its first high-density and high-capacity RRAM chip, named MountTai 2026, which took place on October 12. The company claims this is the world's first RRAM chip of this type featuring high density and large capacity, although this statement has not yet been independently verified. The chip is currently undergoing validation after the tape-out.

The MountTai 2026 chip is designed using a 28nm CMOS process and features a 1T4R cell structure. It provides a capacity of 1 Gbit per chip, achieves a density of 30 Mbit per square millimeter, and has an access latency of less than 20 nanoseconds. Furthermore, the chip incorporates on-chip hardware error correction.

RRAM, or Resistive Random-Access Memory, retains data by changing the material between resistance states and holds it when power is off. In a standard 1T1R configuration, each resistive cell is equipped with its own selector transistor. However, as cell sizes shrink, the area occupied by these transistors and their wiring becomes a limiting factor for density. The 1TnR approach allows one transistor to serve multiple cells, thereby reducing the transistor area per bit; MountTai 2026 uses one transistor for four cells.

Using a shared transistor introduces several issues, including current leakage paths between cells, read and write disturbance, and reliability problems under various operating conditions. MemSilicon states that it has resolved these issues at the circuit level by implementing a negative voltage design and a unified reset scheme to suppress array leakage, multi-voltage wordline drivers that separate high and low voltage read and write paths, adaptive protection polarization to reduce incorrect writes, and an adaptive sensing scheme with tracking that works in conjunction with error correction to improve read yield at gigabit capacity.

The company's technology is based on the work of Liu Min, a fellow of the Chinese Academy of Sciences, who published research on 28nm 1T2R RRAM design in 2020. Since the cells are created in back-end layers compatible with standard CMOS, this method is intended for embedding non-volatile memory into logic chips.

MemSilicon is targeting on-board storage for model weights, KV caches, and parameters in SoCs, edge AI devices, and AI PCs, where SRAM is fast but consumes significant space per bit, and integrating embedded flash memory becomes increasingly difficult as logic processes scale down.

DDR5 RAM Memories on Sale on Amazon for Computer Upgrades
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olhardigital.com.br

DDR5 RAM Memories on Sale on Amazon for Computer Upgrades

If your computer or laptop is slow when running demanding software, it might be time to increase the RAM memory. Three options for DDR5 RAM memories that are on sale on Amazon have been selected, all offering good speed and compatibility for those who want to perform an upgrade without difficulty.

Desktop Option: MACROVIP 8GB 5600MHz DDR5 RAM Module

This option is ideal for those looking to expand the memory of a desktop while maintaining a high level of performance. This module, following the DDR5 standard and operating at 5600MHz, provides a higher transfer rate than previous generations, making it a robust choice for both daily tasks and multitasking.

For laptops, there is an Adata XPG memory in SODIMM format, which operates with a reduced voltage of only 1.1V. This results in more efficient power consumption, which is advantageous for those who prioritize performance without compromising battery life. With CL46 latency and a frequency of 5600MHz, it ensures agile responses in complex applications.

The desktop version of the Adata DDR5 line combines high operating frequency with energy efficiency. Featuring CL46 and compatibility with the latest platforms, it represents a safe alternative for those building or upgrading a PC with modern and quality components.

It is important to note that these offers may disappear at any time, so it is recommended to check each product while they are available. Users should access the links, compare alternatives, and select the one that best suits their current configuration, as the system will benefit from this upgrade.

New Compressed RAM (CRAM) technology for Linux promises significant boost in memory performance
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tecnoblog.net

New Compressed RAM (CRAM) technology for Linux promises significant boost in memory performance

The Compressed RAM (CRAM) project, proposed by engineer Grigory Pris, presents a solution for more efficient memory management in the Linux operating system. Unlike existing technologies ZRAM and Zswap, CRAM treats the compressed area as native RAM, which allows it to avoid using traditional or virtual swap and optimize data access.

At a presentation held at the Linux Plumbers Conference 2026, it was demonstrated that CRAM achieved performance 452 times greater than ZRAM. Grigory Pris's team, an engineer from Meta, introduced a concept capable of making the Linux kernel even more efficient when handling large volumes of data in RAM, especially under memory scarcity.

As the name suggests, CRAM is based on a new approach to compressing data directly in RAM. Although similar methods exist, two standards stand out in Linux: ZRAM and Zswap. Understanding their principles helps assess CRAM's advantages.

ZRAM creates a kind of virtual data block, mimicking a hard drive or SSD within RAM itself. When memory starts filling up, inactive or rarely used memory pages are compressed and moved into this block, thereby reducing RAM consumption. It is important to note that ZRAM functions as a swapping mechanism, using part of disk space as RAM extension, but it does so inside the RAM itself.

Zswap is similar in principle but more advanced. It intercepts attempts by the operating system to send memory pages to the actual swap (on HDD or SSD). Instead, the data of these pages is compressed and placed in specific areas of RAM. Only when memory approaches full capacity are the pages sent to the actual swap.

Despite ZRAM and Zswap being ingenious solutions, they face a potential performance issue. The dynamics of compressing and decompressing data for processing through swaps, whether real or virtual, are significantly slower than operations performed directly with RAM.

This is where CRAM steps in as a solution. Although CRAM superficially resembles ZRAM, the key difference is that in the first case, the block storing compressed data is treated as actual RAM, not as traditional swap. Linux begins to operate on this space as if it were an additional block of RAM, activating native kernel memory management mechanisms to work with the area containing compressed data.

These built-in features allow, under certain circumstances, access to compressed data without triggering a page fault—a situation where the system tries to access a memory page that is unavailable or unmapped, requiring kernel intervention. They also ensure page migration between addresses, reducing the risk of interruptions, among other benefits that positively affect performance.

How much exactly is the performance improved? At the Linux Plumbers Conference (LPC) 2026, Grigory Pris explained that in a specific benchmark, CRAM allowed for 489 million operations per second compared to 1.1 million operations per second for ZRAM. This means that in this test, CRAM was 452 times faster than classic ZRAM, and this was achieved without the need to create entirely new memory management infrastructure in Linux.

Although the level of performance may vary depending on the application, the trend indicates that CRAM will consistently demonstrate superior results. The project is promising, but excessive enthusiasm should be tempered, as CRAM development is not yet complete, and there is no planned official release date. It should also be noted that such a solution is likely to be geared towards professional applications running on servers, although it could potentially be useful for home use as well.

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