October 21, 04:55Pandaily

UltraRISC Unveils RISC-V UR-CP400 Core with RVA23 Support and 8-Way Out-of-Order Execution

UltraRISC Technology, a Shanghai-based company, demonstrated the UR-CP400 processor core IP. This core conforms to the RVA23 profile, features 8-way out-of-order execution, and was presented at the sixth RISC-V Summit in China, held in Shenzhen from October 18 to 20.

The company plans to deliver this development to clients in the first quarter of 2027. It is important to note that UR-CP400 is an IP core, not a finished chip; UltraRISC licenses its cores to chip developers who then integrate them into their own processors, and also uses them in its proprietary CPU products.

According to UltraRISC statements, the core adheres to the RVA23 profile—a RISC-V application standardizing the feature set expected by major operating systems and software. It also supports version 1.0 of the RISC-V vector extension. The core's microarchitecture is implemented out-of-order with 8-way issue and a 14-stage pipeline.

On a prototype built on FPGA, the company achieved a SPECint2006 score above 22 instructions per gigahertz. This figure was obtained in an FPGA emulation configuration, not on finished silicon. At the summit, UltraRISC showcased an FPGA-based system demonstrating this prototype. While FPGA results are a useful early indicator of performance per clock cycle, they do not provide a direct representation of the final product's clock speeds, power consumption, or memory performance.

For comparison, the earlier UR-CP100 core, used in the eight-core UR-DP1000 desktop CPU, was rated by the company at 10.4 instructions per gigahertz according to the single-core SPECint2006 test. If the new metric holds true in silicon, UR-CP400 more than doubles the integer performance per clock compared to the previous generation.

Furthermore, UltraRISC claims that UR-CP400 includes virtualization enhancements for multi-level cloud environments, is designed to support server CPU platforms, and contains hardware optimizations aimed at agent AI workloads. The company did not provide detailed information regarding the specifics of these AI-related changes.

CTO Jian Jian presented the UR series and the latest advancements of the UR-CP400 architecture at the Data Center and High-Performance Computing Forum during the summit. Alongside the new core, UltraRISC demonstrated system solutions built on UR-DP1000, including edge AI installations, multi-node clusters, and virtualization.

The launch of UR-CP400 coincided with a busy week for high-end RISC-V development in China, as several companies used the summit to showcase server and automotive cores. It should be emphasized that all stated performance metrics are company claims and have not undergone independent testing.

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pandaily.comOctober 14, 10:40

MemSilicon introduced the MountTai 2026 RRAM chip with a 1T4R architecture

The Chinese memory startup MemSilicon announced the completion of the tape-out process for its first high-density and high-capacity RRAM chip, named MountTai 2026, which took place on October 12. The company claims this is the world's first RRAM chip of this type featuring high density and large capacity, although this statement has not yet been independently verified. The chip is currently undergoing validation after the tape-out.

The MountTai 2026 chip is designed using a 28nm CMOS process and features a 1T4R cell structure. It provides a capacity of 1 Gbit per chip, achieves a density of 30 Mbit per square millimeter, and has an access latency of less than 20 nanoseconds. Furthermore, the chip incorporates on-chip hardware error correction.

RRAM, or Resistive Random-Access Memory, retains data by changing the material between resistance states and holds it when power is off. In a standard 1T1R configuration, each resistive cell is equipped with its own selector transistor. However, as cell sizes shrink, the area occupied by these transistors and their wiring becomes a limiting factor for density. The 1TnR approach allows one transistor to serve multiple cells, thereby reducing the transistor area per bit; MountTai 2026 uses one transistor for four cells.

Using a shared transistor introduces several issues, including current leakage paths between cells, read and write disturbance, and reliability problems under various operating conditions. MemSilicon states that it has resolved these issues at the circuit level by implementing a negative voltage design and a unified reset scheme to suppress array leakage, multi-voltage wordline drivers that separate high and low voltage read and write paths, adaptive protection polarization to reduce incorrect writes, and an adaptive sensing scheme with tracking that works in conjunction with error correction to improve read yield at gigabit capacity.

The company's technology is based on the work of Liu Min, a fellow of the Chinese Academy of Sciences, who published research on 28nm 1T2R RRAM design in 2020. Since the cells are created in back-end layers compatible with standard CMOS, this method is intended for embedding non-volatile memory into logic chips.

MemSilicon is targeting on-board storage for model weights, KV caches, and parameters in SoCs, edge AI devices, and AI PCs, where SRAM is fast but consumes significant space per bit, and integrating embedded flash memory becomes increasingly difficult as logic processes scale down.

pandaily.comOctober 8, 10:45

Huawei introduces experimental file system XMFS for inter-node memory sharing at LPC 2026

Engineers from Huawei demonstrated an experimental file system called XMFS at the Linux Plumbers Conference (LPC) in Prague on October 5th. This was reported by IT Home on October 8th.

XMFS, which stands for eXpress Memory FS, is designed for Linux-based servers that utilize either the standard CXL 3.0 or Huawei's unified bus. The primary goal of the system is to allow applications to access shared memory on other nodes via standard POSIX file calls, thereby avoiding the need to rewrite higher-level software.

Conceptual Features of XMFS

Conference materials describe XMFS as a kernel prototype. The system explores the possibility of placing memory distributed across servers as a storage layer within Linux, rather than having each application access it through its own interface. What distinguishes XMFS from other memory sharing and CXL file systems like FAMFS and DAXFS is that it does not place the standard POSIX interface at the center.

In principle, existing programs could open, read, and write this remote memory just as they do with regular files.

Testing Results and Open Issues

Huawei reported at the conference that it conducted preliminary tests on workloads with a large amount of metadata, as well as when exchanging container images between nodes. These tests are viewed by the team as an indicator of the approach's viability, rather than a product benchmark. The team also listed several unresolved issues: maintaining filesystem metadata synchronization between nodes, ensuring cache coherence without hardware support, unifying semantic memory links and RDMA into a single transport, and managing multi-tiered capacity located across multiple machines.

Code has begun to appear, but currently only for openEuler. A version-8 patch placed in the openEuler kernel mailing list in August affects 15 new or modified files, covering the core logic of the file system, directories, files, inodes, journaling, garbage collection, and URMA support. It is important to note that this is not a submission to the main Linux kernel. XMFS has not undergone formal review by the main kernel, and conference materials refer to it as a prototype for exploring the idea, not a ready-to-merge file system.

Currently, XMFS represents research within Huawei's interconnect software stack. It is not a commercial file system nor is it part of the Linux kernel.