The Chinese memory startup MemSilicon announced the completion of the tape-out process for its first high-density and high-capacity RRAM chip, named MountTai 2026, which took place on October 12. The company claims this is the world's first RRAM chip of this type featuring high density and large capacity, although this statement has not yet been independently verified. The chip is currently undergoing validation after the tape-out.
The MountTai 2026 chip is designed using a 28nm CMOS process and features a 1T4R cell structure. It provides a capacity of 1 Gbit per chip, achieves a density of 30 Mbit per square millimeter, and has an access latency of less than 20 nanoseconds. Furthermore, the chip incorporates on-chip hardware error correction.
RRAM, or Resistive Random-Access Memory, retains data by changing the material between resistance states and holds it when power is off. In a standard 1T1R configuration, each resistive cell is equipped with its own selector transistor. However, as cell sizes shrink, the area occupied by these transistors and their wiring becomes a limiting factor for density. The 1TnR approach allows one transistor to serve multiple cells, thereby reducing the transistor area per bit; MountTai 2026 uses one transistor for four cells.
Using a shared transistor introduces several issues, including current leakage paths between cells, read and write disturbance, and reliability problems under various operating conditions. MemSilicon states that it has resolved these issues at the circuit level by implementing a negative voltage design and a unified reset scheme to suppress array leakage, multi-voltage wordline drivers that separate high and low voltage read and write paths, adaptive protection polarization to reduce incorrect writes, and an adaptive sensing scheme with tracking that works in conjunction with error correction to improve read yield at gigabit capacity.
The company's technology is based on the work of Liu Min, a fellow of the Chinese Academy of Sciences, who published research on 28nm 1T2R RRAM design in 2020. Since the cells are created in back-end layers compatible with standard CMOS, this method is intended for embedding non-volatile memory into logic chips.
MemSilicon is targeting on-board storage for model weights, KV caches, and parameters in SoCs, edge AI devices, and AI PCs, where SRAM is fast but consumes significant space per bit, and integrating embedded flash memory becomes increasingly difficult as logic processes scale down.